CS302 - Digital Logic Design

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1A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register1248D
2In a sequential circuit the next state is determined by ________ and _______State variable, current stateCurrent state, flip-flop outputCurrent state and external inputInput and clock signal appliedC
3The divide-by-60 counter in digital clock is implemented by using two cascading countersMod-6, Mod-10Mod-50, Mod-10Mod-10, Mod-50Mod-50, Mod-6A
4In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintainedTrueFalse  A
5The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flopSet-up timeHold timePulse Interval timePulse Stability time (PST)B
674HC163 has two enable input pins which are _______ and _________ENP, ENTENI, ENCENP, ENCENT, ENIA
7____________ is said to occur when multiple internal variables change due to change in one input variableClock SkewRace conditionHold delayHold and WaitB
8The _____________ input overrides the ________ inputAsynchronous, synchronousSynchronous, asynchronousPreset input (PRE), Clear input (CLR)Clear input (CLR), Preset input (PRE)A
9A decade counter is __________Mod-3 counterMod-5 counterMod-8 counterMod-10 counterD
10In asynchronous transmission when the transmission line is idle, _________It is set to logic lowIt is set to logic highRemains in previous stateState of transmission line is not used to start transmissionB
11Excess-8 code assigns _______ to “-8”1110110010000000D
12The voltage gain of the Inverting Amplifier is given by the relation ________Vout / Vin = - Rf / RiVout / Rf = - Vin / RiRf / Vin = - Ri / VoutRf / Vin = Ri / VoutA
13LUT is acronym for _________Look Up TableLocal User TerminalLeast Upper Time PeriodNone of given optionsA
14Addition of two octal numbers “36” and “71” results in ________213123127345C
15___________ is one of the examples of synchronous inputsJ-K inputEN inputPreset input (PRE)Clear Input (CLR)A
16__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delayRace conditionClock SkewRipple EffectNone of given optionsB
17In a state diagram, the transition from a current state to the next state is determined byCurrent state and the inputsCurrent state and outputsPrevious state and inputsPrevious state and outputsA
18________ is used to simplify the circuit that determines the next stateState diagramNext state tableState reductionState assignmentD
19The three fundamental gates are ___________AND, NAND, XOROR, AND, NANDNOT, NOR, XORNOT, OR, ANDD
20The total amount of memory that is supported by any digital system depends upon ______The organization of memoryThe structure of memoryThe size of decoding unitThe size of the address bus of the microprocessorD
21Stack is an acronym for _________FIFO memoryLIFO memoryFlash MemoryBust Flash MemoryB
23Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)1100001100001111C
24The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________Doesn’t have an invalid stateSets to clear when both J = 0 and K = 0It does not show transition on change in pulseIt does not accept asynchronous inputsA
25A multiplexer with a register circuit converts _________Serial data to parallelParallel data to serialSerial data to serialParallel data to parallelB
26A GAL is essentially a ________Non-reprogrammable PALPAL that is programmed only by the manufacturerVery large PALReprogrammable PALD
27in ____________, all the columns in the same row are either read or writtenSequential AccessMOS AccessFAST Mode Page AccessNone of given optionsC
28In order to synchronize two devices that consume and produce data at different rates, we can use _________Read Only MemoryFist In First Out MemoryFlash MemoryFast Page Access Mode MemoryB
29A positive edge-triggered flip-flop changes its state when ________________Low-to-high transition of clockHigh-to-low transition of clockEnable input (EN) is setPreset input (PRE) is setA
30A frequency counter ______________Counts pulse widthCounts no. of clock pulses in 1 secondCounts high and low range of given clock pulseNone of given optionsB
31Flip flops are also called _____________Bi-stable dualvibratorsBi-stable transformerBi-stable multivibratorsBi-stable singlevibratorsC
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